1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof, in particular, to a semiconductor device and a fabrication method thereof including a MOS transistor.
2. Description of the Related Art
Up to now, the following measures have been achieved about control of a flat band voltage VFB or a threshold voltage Vth of Complementary Metal Insulator Semiconductor Field Effect Transistors (CMISFETs) having a high permittivity (High-k) layer.
That is, a first method is a method of using an independent gate electrode material in n-channel MISFETs and p-channel MISFETs (e.g., refer to Patent Document 1 and Patent Document 2). The patent document 1 discloses an example, which applies NiSi as a gate electrode of n-MISFETs and Ni3Si as a gate electrode of p-MISFETs. Furthermore, the patent document 2 discloses an example, which applies NiSi as a gate electrode of n-MISFETs and Pt as a gate electrode of p-MISFETs. Fundamentally, selection of the gate electrode is achieved so that a work function of an n-MIS gate becomes lower than a work function of a p-MIS gate. However, Ni silicide material is sensitive to annealing temperature, and the composition ratio (stable phase) changes easily. Moreover, since Pt series material is reducing material, the Pt series material is sensitive to annealing temperature and atmosphere, and changes the character of an underlying insulating film. For this reason, the annealing condition after electrode formation is restrained.
A second method is a method of inserting an La2O3 layer to n-MIS and inserting an Al2O3 layer to p-MIS as a independent capping layer for a gate electrode/high permittivity (High-k) layer interface, in n-channel MISFETs and p-channel MISFETs (e.g., refer to Non-Patent Document 1, Non-Patent Document 2, and Non-Patent Document 3). The capping layer is inserted in order to ease or remove the FLP (Fermi Level Pinning) phenomenon in the gate electrode/high permittivity (High-k) layer interface. However, even when using the capping layer, in order to shift a flat band voltage VFB, an interface with a high permittivity (High-k) layer/gate insulating film (SiO2) is important, and the diffusion process to the interfacial region must be used.
A third method is a method to set up so that a threshold voltage Vth of n+ polysilicon gate and p+ polysilicon gate may become symmetrical by controlling Al concentration in a high permittivity (High-k) gate insulating film, in n-MISFETs and p-MISFETs (e.g., refer to Patent Document 3). However, the concentration range where the symmetry of the threshold voltage Vth is obtained by Al concentration is dramatically narrow, and it is anxious about degradation of the electrical characteristics by Al introduction to n-MISFETs.
[Patent Document 1] JP, 2007-80955, A (pp. 11-14, and FIG. 1)
[Patent Document 2] JP, 2006-80133, A (pp. 8-9, and FIG. 1)
[Patent Document 3] JP, 2006-278376, A (pp. 7-8, and FIG. 4)
[Non-Patent Document 1] H. N. Alshareef et al., “Thermally Stable N-Metal Gate MOSFETs Using La-Incorporated HfSiO Dielectric”, 2006 Symposium on VLSI Technology Digest of Technical Papers, pp. 10-11.
[Non-Patent Document 2] Hyung-Suk Jung et al., “Dual High-k Gate Dielectric Technology Using AlOx Etch (SAE) Process with Nitrogen and Fluorine Incorporation”, 2006 Symposium on VLSI Technology Digest of Technical Papers, pp. 204-205.
[Non-Patent Document 3] K. L. Lee et al., “Poly-Si/AlN/HfSiO stack for ideal threshold voltage and mobility in sub-100 nm MOSFETs”, 2006 Symposium on VLSI Technology Digest of Technical Papers, pp. 202-203.